1. Field of the Invention
The present invention relates to a non-volatile memory device and, more particularly, to a non-volatile memory device which can prevent a program failure from occurring in an overwriting process of an electrically erasable programmable read only memory (EEPROM).
2. Brief Description of the Background Art
Different from SRAM or DRAM, an electrically erasable programmable read only memory (EEPROM) cell is a non-volatile memory cell useful for electrically erasing, storing and maintaining data without a power supply. Recently, EEPROM cells have been utilized in a variety of applications.
An EEPROM cell is classified as either a flash type memory device comprising a single cell with one transistor or a floating gate tunnel oxide type (FLOTOX) device comprising a single cell with two transistors. The former type of cell, constructed with one transistor, has an advantage in that a unit cell has a small size. The disadvantage of the one transistor cell is that it exhibits low product reliability when compared with the two transistor cell, i.e., the FLOTOX type of cell.
The FLOTOX type EEPROM memory cell has been used in smart card IC products world wide. FIGS. 1 and 2 illustrate a structure of the FLOTOX type cell. FIG. 1 is a layout diagram illustrating the structure of a memory cell of an EEPROM device. FIG. 2 is a cross-sectional view illustrating the structure along line X-X' in FIG. 1.
According to FIGS. 1 and 2, a conventional FLOTOX type EEPROM cell comprises a gate insulating layer 12 formed at an active area A of a p-type semiconductor substrate 10 to partially expose the surface of a substrate for a tunnel oxide layer 16. The tunnel oxide layer 16 is thinner than the gate insulating layer 12 which is formed at the partially exposed surface of the substrate 10 of the active area. A sense transistor I is constructed via a deposition method. The sense transistor I comprises a first conductivity layer 18, an interlevel insulating layer 20, and a second conductivity layer 22. It is positioned near the neighboring gate insulating layer 12 and the tunnel oxide layer 16. A select transistor II includes a gate having a second conductivity layer 22a positioned near the gate insulating layer 12 beside the sense transistor I. A n-type junction 14 is constructed inside the substrate 10 under the tunnel oxide layer 16 to overlap with a predetermined portion of the select transistor II. A source 24, made using a n-/n+ double junction structure, is inside the substrate 10 and is positioned at a predetermined distance from one side of the junction 14 for to overlap with a predetermined portion of the sense transistor I. A drain 26, made using a n-/n+ double junction structure, is inside the substrate 10 and is positioned at a predetermined distance from the other side of the junction 14 for to overlap with a predetermined portion of the select transistor II.
The junction 14 comprises a first n-type junction 14a of medium density positioned inside the substrate 10 below the oxide layer 16. The junction 14 further comprises a second n-type junction 14b of low density in contact with the first junction 14a and partially overlapping with the select transistor II. The first conductivity layer 18 is used as a floating gate. The second conductivity layer 22 is used as a control gate. Also, the second conductivity layer 22a is used as a select gate.
Referring again to FIGS. 1 and 2, symbols A and C represent the active area of the substrate 10 and a bit line contact forming zone, respectively.
The erasing and programming method of the EEPROM cell is described below.
The method of erasing the EEPROM cell will now be described. First a high voltage (Vpp=15V through 20V) is applied to the control gate (the second conductivity layer 22), which is used as a sense line. Then a 0V potential is applied to the bit line (drain 26). While the source 24, being used as a common ground line, is kept floating (or 0V), a high voltage (Vpp=15V through 20V) is applied to the select gate (the second conductivity layer 22a), being used as a word line, thereby creating a strong electric field which is applied to the control gate and the bit line. As a result, the blocking wall of the tunnel oxide layer 16 gets thinner, which in turn enables some of the electrons, supplied from the bit line in the FN tunnel method as they pass through the oxide layer 16, to charge into the floating gate (the first conductivity layer 18).
Likewise, if electrons fill inside the floating gate, the threshold voltage Vth of the sense transistor rises higher by 3 to 7V or so because of stored electrons. If a supply voltage is applied to the select gate, the control gate and the bit line, in order to read the cell, the higher threshold voltage Vth results in a failure to form a channel in order to stop the current from flowing. Consequently, a first state, the "off state", of the cell is memorized.
The programming process of the EEPROM cell will now be described. First a threshold voltage Vth is applied to the control gate (the second conductivity layer 22), which is being used as the sense line. Then a high voltage (Vpp=15V through 20V) is applied to the bit line (drain 26). While the source 24, used as the common grounding line, is kept floating, a high voltage (Vpp =15 through 20V) is applied to the select gate (the second conductivity layer 22a), which is used as a word line, thereby creating a strong electric field which is applied to both ends of the tunnel oxide layer 16, between the floating gate (the first conductivity layer indicated by reference numeral 18) and the substrate 10. As a result, the blocking wall of the tunnel oxide layer 16 gets thinner and thereby enables the electrons stored in the floating gate to migrate through the blocking wall of the thinner oxide layer 16, via the FN tunnel method, at one time and are discharged out to the drain 26. As electrons migrate from the floating gate, the Vth of the sense transistor is lowered by a range of -4V to -1V, or so. If a supply voltage is applied to the select gate, which is being used as a word line to read the cell, the low threshold voltage Vth causes a channel to form in order to allow current flow. Consequently, a second state, the "on state", of the cell is memorized.
The erasing process, relevant to an electron charging process, is simultaneously performed by a unit of 1 byte (8 bits) or 1 page (32 through 64 bits). The programming process, relevant to the electron discharging process, is performed in a method to discharge the electrons in a selected cell.
For a better understanding of the prior art, reference is made to FIG. 3. FIG. 3 shows a circuit diagram of memory cells for an EEPROM device. The EEPROM device includes a unit cell which was fabricated in accordance with the structure of FIG. 2. In the circuit diagram, reference symbols S and D, respectively, indicate a source being used as a grounding line and a drain being connected with the bit line. The word line, the sense line and the bit line are respectively designated by symbols W/L (W/L1, W/L2 . . . ), S/L (S/L1, S/L2 . . . ) and B/L (B/L1, B/L2 . . . ).
However, in accordance to the prior art, an EEPROM device having a memory cell being constructed in the above manner will have problems in the overwriting process. That is, problems in the process of performing another programming process to erased the "off state" of a cell and to memorize another data input after a programming process is performed. If an erased "off state" of the cell 5 is programmed again with a programmed "on state" of cell 1 being kept at the same word line (W/L1), a high voltage (Vpp=15V to 20V) is applied to the B/L5 and W/L1 of the selected cell 5 and a 0V should be applied to the S/L1 and B/L (B/L1, B/L2, B/L3, B/L4, B/L 6) of the unselected cells. In this case a current path is formed through source (S) and cell 1, which become the common grounding line, thereby cause a programming failure of the programming process for cell 5.
In order to prevent the above functional programming failure of cell 5, the memory cells are erased by a unit of 1 byte (8 bits) or 1 page (32 through 64 byte), and only a selected cell should be programmed. However, if the overwriting process is performed in this programming method, there may be operational failures in the EEPROM device as it is now operating in a mode different from the programming process desired by a programmer.
Therefore, the aforementioned programming method of the EEPROM device can not be used effectively.